Senior Design Verification Engineer
1 settimana fa
Principal Recruitment Consultant at IC Resources - Semiconductor Engineering divisionI am seeking a highly experienced Senior Verification Engineer to join a leading organisation at the forefront of semiconductor innovation.This is an exceptional opportunity to be part of a dynamic and multicultural team, working on cutting-edge SoC designs that will shape the future of AI, HPC, and other advanced technologies.Required Skills & ExperienceMaster's degree in a relevant field.Proven experience in 3 successful tapeoutsExpertise in UVM/System VerilogExperience with Formal VerificationExperience with scripting languages such as Python, Perl or BashKnowledge of NoC, PCIe, DDR and other standard peripherals is desirable but not essentialThis Senior Verification Engineer role offers a unique opportunity to contribute to game-changing semiconductor technology, with the flexibility of a hybrid working model in either Ghent, Barcelona or Rome.Tel -#J-*****-Ljbffr
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Senior Design Verification Engineer
2 settimane fa
Lazio, Italia Ic Resources A tempo pienoSenior Design Verification Engineer - RomeI am seeking a highly experienced Senior Verification Engineer to join a leading organisation at the forefront of semiconductor innovation.This is an exceptional opportunity to be part of a dynamic and multicultural team, working on cutting-edge So C designs that will shape the future of AI, HPC, and other advanced...
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Design Verification Engineer
6 giorni fa
Lazio, Italia Altro A tempo pienoDesign Verification Engineer needed for digital chip SOCs for satellite communications.Requires experience in UVM and digital verification.
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Senior Formal Verification Engineer
4 giorni fa
Lazio, Italia Openchip & Software Technologies A tempo pienoAs a Senior Formal Verification Engineer, you will contribute to defining and leading the formal verification strategy for our systems.ResponsibilitiesWork closely with system architects and design team to establish formal verification environment and settingGuide the use of formal verification that correct formal techniques are used appropriately to improve...
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Senior Formal Verification Engineer...
20 ore fa
Lazio, Italia Openchip & Software Technologies A tempo pienoAs a Senior Formal Verification Engineer, you will contribute to defining and leading the formal verification strategy for our systems.Responsibilities- Work closely with system architects and design team to establish formal verification environment and setting- Guide the use of formal verification that correct formal techniques are used appropriately to...
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Senior Verification Engineer: Soc
6 giorni fa
Lazio, Italia Openchip And Software Technologies Sl A tempo pienoA technology firm in Rome seeks a Senior Functional Verification Engineer who will interface with architecture, design, physical implementation, and software teams.You will develop verification environments and execute verification plans using SystemVerilog and UVM.The ideal candidate has a Master's degree, 7+ years of relevant experience, and strong...
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Principal Engineer
1 settimana fa
Lazio, Italia Analog Devices A tempo pienoAbout Analog Devices, Inc. (ADI)'s Trinamic motor and motion control products transform digital information into precise physical motion, enabling Industry 4.0 performance in applications such as advanced robotics, automation, medical prosthetics, 3D printing, and more.The ADI Trinamic motor control ICs represent complete, efficient, small-footprint...
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Senior Engineer Functional Verification
6 giorni fa
Lazio, Italia Altro A tempo pienoThe Role : As a Senior Functional Verification Engineer you will be interfacing with architecture design physical implementation and software teams in order to make sure that the systems are performing to the highest level.Your work may involve high-level modelling UVM HW / SW Co-Debug Simulation Acceleration support.Key Responsibilities :Reading and...
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Senior Formal Verification Engineer
20 ore fa
Lazio, Italia Openchip & Software Technologies A tempo pienoThe Role: As a Senior Formal Verification Engineer, you will contribute to defining and leading the formal verification strategy for our systems.Responsibilities:- Work closely with system architects and design team to establish formal verification environment and setting- Guide the use of formal verification so that correct formal techniques are used...
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Design Verification Engineer
1 settimana fa
Lazio, Italia Altro A tempo pienoDesign Verification Engineer - VLSI/ASIC/FPGA Hardware Experience:3 - 25 YearsLocation:Permanent Remote anywhere in the WorldContract Length:6 MonthsType:Full time contract (8 hrs/day) Overlap Hours: 4 hrs/day with PSTMandatory Skills:Overall - 5 years of experience.Minimum of 2 years of relevant experience in Hardware Design and/or Hardware...
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Senior Ams Verification Engineer
6 giorni fa
Lazio, Italia Analog Devices A tempo pienoAbout Analog Devices Analog Devices, Inc. (NASDAQ : ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge.ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change,...