Lavori attuali relativi a ASIC Digital Design, Staff Engineer - Pavia - Synopsys
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ASIC Digital Design, Staff Engineer
2 settimane fa
Pavia, Italia Synopsys A tempo pienoWe are seeking a highly motivated and innovative digital design engineer with knowledge of ASIC development flow. The candidate would be working as part of a highly experienced mixed-signal design and verification team, targeting the current and next generation PAM-based SerDes products. Strong theoretical and practical background in high-speed serializer...
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ASIC Digital Design, Staff Engineer
3 settimane fa
Pavia, Italia Synopsys A tempo pienoWe are seeking a highly motivated and innovative digital design engineer with knowledge of ASIC development flow. The candidate would be working as part of a highly experienced mixed-signal design and verification team, targeting the current and next generation PAM-based SerDes products. Strong theoretical and practical background in high-speed serializer...
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ASIC Digital Design Engineer, Staff
1 settimana fa
Pavia, Italia Synopsys A tempo pienoWe are seeking a highly motivated and innovative digital design engineer with knowledge of ASIC development flow. The candidate would be working as part of a highly experienced mixed-signal design and verification team, targeting the current and next generation PAM-based SerDes products. Strong theoretical and practical background in high-speed serializer...
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Digital Design Engineer
3 settimane fa
Pavia, Lombardia, Italia Synopsys A tempo pieno{"h1": "Senior Digital Design Engineer", "p": "We are seeking a highly motivated and innovative digital design engineer with expertise in ASIC development flow. The ideal candidate will work as part of a highly experienced mixed-signal design and verification team, targeting the current and next generation PAM-based SerDes products. Strong theoretical and...
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ASIC Digital Design, Sr Engineer
7 giorni fa
Pavia, Italia Synopsys A tempo pienoSeeking a highly motivated and innovative design engineer with background in high-speed protocols. Working as part of an experienced digital design and verification team. The position offers an excellent opportunity to work with experts on several fields. The candidate will be involved at specify, design and implement phases of state-of-the-art products.Key...
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ASIC Digital Verification, Sr Staff Engineer
3 settimane fa
Pavia, Italia Synopsys A tempo pienoWe are seeking a highly motivated and innovative digital verification engineer with exceptional knowledge in the verification of high-speed digital designs. The candidate would be working as part of a highly experienced mixed-signal design and verification team, and will be involved in verifying current and next generation PAM-based SerDes products.The...
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ASIC Digital Verification, Sr Staff Engineer
3 settimane fa
Pavia, Italia Synopsys A tempo pienoWe are seeking a highly motivated and innovative digital verification engineer with exceptional knowledge in the verification of high-speed digital designs. The candidate would be working as part of a highly experienced mixed-signal design and verification team, and will be involved in verifying current and next generation PAM-based SerDes products.The...
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Digital Design Engineer
2 settimane fa
Pavia, Italia Inventvm Semiconductor A tempo pienoFrom Master Thesys or PhD sponsorship to taking the next step forward in your career: if you are interested in learning more, send your resume to careers@inventvm.com INVENTVM is actively seeking a Senior Digital Design Engineer to design and develop high-speed and low power digital circuits for the digital signal processing core and control logic of...
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Digital Design Engineer
3 settimane fa
Pavia, Italia Inventvm Semiconductor A tempo pienoFrom Master Thesys or PhD sponsorship to taking the next step forward in your career: if you are interested in learning more, send your resume to careers@inventvm.com INVENTVM is actively seeking a Senior Digital Design Engineer to design and develop high-speed and low power digital circuits for the digital signal processing core and control logic of...
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Digital Verification Engineer
3 settimane fa
Pavia, Lombardia, Italia Synopsys A tempo pienoJob Title: ASIC Digital Verification Sr EngineerWe are seeking a highly skilled digital verification engineer to join our team at Synopsys. As a key member of our mixed-signal design and verification team, you will be responsible for verifying high-speed digital designs and contributing to the development of innovative verification solutions.Main...
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Analog Design, Staff Engineer
3 giorni fa
Pavia, Italia Synopsys A tempo pienoWe're looking for an Analog Design Engineer, Staff to join our team. Does this sound like a good role for you?In this role, you will work on the design, development, and refinement of Multi-Gbps PAM4 SERDES IP. You will be part of a fast-growing analog and mixed signal R&D team, developing high speed analog integrated circuits in the latest FinFET process...
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ASIC Digital Verification Sr Engineer
3 settimane fa
Pavia, Italia Synopsys A tempo pienoWe are seeking a highly motivated and innovative digital verification engineer with exceptional knowledge in the verification of high-speed digital designs. The candidate would be working as part of a highly experienced mixed-signal design and verification team and will be involved in verifying current and next generation PAM-based SerDes products.The...
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Digital Verification, Staff Engineer
3 settimane fa
Pavia (PV), Italia Synopsys A tempo pienoWe are seeking a highly motivated and innovative digital design engineer with knowledge of ASIC development flow. The candidate would be working as part of a highly experienced mixed-signal design and verification team, targeting the current and next generation PAM-based SerDes products. Strong theoretical and practical background in high-speed serializer...
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Digital Verification Engineer, Sr. Staff
3 settimane fa
Pavia, Italia Synopsys A tempo pienoSynopsys is seeking for a highly motivated and innovative digital verification engineer with exceptional knowledge in the verification of high-speed digital designs. The candidate would be working as part of a highly experienced mixed-signal design and verification team and will be involved in verifying current and next generation PAM-based SerDes products....
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Digital Verification Engineer, Sr. Staff
3 settimane fa
Pavia, Italia Synopsys A tempo pienoSynopsys is seeking for a highly motivated and innovative digital verification engineer with exceptional knowledge in the verification of high-speed digital designs. The candidate would be working as part of a highly experienced mixed-signal design and verification team and will be involved in verifying current and next generation PAM-based SerDes products....
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Digital Backend Design Engineer
4 giorni fa
Pavia (PV), Italia Inventvm Semiconductor A tempo pienoFrom Master Thesys or PhD sponsorship to taking the next step forward in your career: if you are interested in learning more, send your resume to INVENTVM is actively seeking a Digital Backend Design Engineer with previous experience in IC digital design implementation flows for state-of-the-art products and technologies. Responsibilities: Implement full...
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Layout Design, Sr Staff Engineer
2 settimane fa
Pavia, Italia Synopsys A tempo pienoAs Layout Design Sr Staff Engineer you will contribute in the development of advanced analog integrated circuit designs using best-in-class Synopsys suite of tools. You will be working with local and global teams in developing layout for complex mixed-signal designs in the latest technology nodes.In your role you will be responsible for taking on top-level...
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Layout Design, Sr Staff Engineer
3 settimane fa
Pavia, Italia Synopsys A tempo pienoAs Layout Design Sr Staff Engineer you will contribute in the development of advanced analog integrated circuit designs using best-in-class Synopsys suite of tools. You will be working with local and global teams in developing layout for complex mixed-signal designs in the latest technology nodes.In your role you will be responsible for taking on top-level...
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Digital Verification Engineer
3 settimane fa
Pavia, Lombardia, Italia Synopsys A tempo pienoSenior Digital Verification EngineerWe are seeking a highly skilled and innovative digital verification engineer to join our team at Synopsys. As a key member of our mixed-signal design and verification team, you will be responsible for verifying current and next-generation PAM-based SerDes products.Main Responsibilities:Design and develop modular...
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Analog Design Engineer
2 settimane fa
Pavia, Italia Inventvm Semiconductor A tempo pienoFrom Master Thesys or PhD sponsorship to taking the next step forward in your career: if you are interested in learning more, send your resume to careers@inventvm.com INVENTVM is actively seeking a Senior Analog Design Engineer to design audio and/or power management circuit blocks using state-of-the-art IC design methodologies and design flows....
ASIC Digital Design, Staff Engineer
2 mesi fa
The PHY IP development is very dynamic and provides an endless list of challenges. The candidate would have an initial training done by the top experts in the field as well as continuous on the job training and assignments. The work is very challenging, not only given the constant technological changes but also given the ownership and the need to charter unknown waters.
Key Qualifications:BSEE or MSEE plus a minimum of 4 years of digital design and verification experience in the industryGood experience in writing block-level test-cases including constrained directed random testsMust be familiar with Verilog and VCS. Good knowledge of back-end synthesis tools DC/PT is requiredMust have knowledge of digital design methodologies, ATE production testing, DFT insertion, Synthesis constraints and flowsScripting experience in Shell, Perl, Python and TCL is a plusGood theoretical and practical understanding of digital signal processing and data recovery circuits is requiredGood communication skills for interacting between different design groups and customer support teams are requiredMust be self-motivated, proactive, and able to balance good design quality while meeting tight deadlinesResolves issues in creative ways and exercises independent judgment in selecting methods and techniques to obtain solutionsMay guide more junior peers with aspects of their job. Networks with senior internal and external personnel in own area of expertiseMust exhibit ability to produce good results as an individual and team contributor Preferred Experience:RTL coding, modeling of analog blocks, and writing complex system-level test-benches in VerilogDefining synthesis design constraints and resolving STA issues as well as gate-level simulation failuresDefining Clock/Reset domain crossing design constraints and evaluating violations using CDC/RDC toolsEnhancing and maintaining existing SERDES PHY IPs supporting multiple protocolsInteracting with Application Engineers for customer support and resolving technical issues with Analog and P&R teams
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